VLSI based project

  • VLSI architecture and chip for combined invisible robust and fragile watermarking
  • FPGA implementation of the 32-bit CRC project
  • Operation improvement of indoor robot
  • FPGA implementation JPEG 2000 using 2-D DWT 
  • Implementation of the I2C interface
  • FPGA implementation of the 12-bit Ternary multiple
  • VLSI design of rank order filtering using DVRAM
  • A low power digital-based reconfigurable FIR filter
  • VLSI design heart model
  • Speed optimization of FPGA based modified Viterbi decoder
  • Timing error tolerance in small core designs for SoC application
  •  Partially parallel encoder architecture for long polar codes
  • Verilog implementation of the RSA cryptography algorithm.
  • A VLSI  based robot dynamics learning algorithm
  • Implementation of DCT & IDCT technique on image compression using VERILOG HDL
  • Implementation of pipelined AES algorithm on the FPGA (Xilinx) kit.
  • Dual data-rate SD RAN controller
  • Enhanced memory reliability against multiple cell upsets using decimal matrix code
  • Image compression technique with a discrete wavelet transform technique applied by Verilog for the efficient use of the area.
  • A fast application based supply voltage optimization method for dual voltage FPGA
  • Ultra High throughput low-power packet classification
  • Low power pulse triggered flipflop design based on a signal feed-through
  • Shift register design using the two-bit flip-flop
  • Efficient on-chip crosstalk avoidance by using codec design
  • Design of CMOS operational amplifier in submicron technology